Modern digital processors, such as computers, usually require a means of storing digital information for later use. Various well-known methods of storing and retrieving information are available to the designer. However, when the application requires that digital information be temporarily stored for subsequent quick retrieval, Random Access Memory (RAM) is generally used.
A RAM device generally consists of one or more semiconductor devices which store digital information in address locations. A RAM device must provide a means for storing data, a means for writing (WRITE) data into particular cells at selected address locations, and a means for reading (READ) the data stored in the cells at particular address locations.
The basic digital storage element of a RAM device is a bit-cell. A single bit-cell can store one bit of digital data. By connecting a bit-cell to circuitry for writing and reading the bit-cell data, a cell is formed. By connecting many cells to address circuitry, the RAM device itself is formed.
The conventional bit-cell itself is a flip-flop circuit. A flip-flop is usually formed by two transistors arranged in a complimentary, cross-coupled configuration. A bit-cell can store information in one of two possible logic states. The first logic state corresponds to a first flip-flop transistor conducting. The second logic state corresponds to conduction by the second flip-flop transistor. In each case only one of the complimentary transistors is conducting.
In many applications it is desirable for the logic state of the bit-cell to switch from one state to the other as rapidly as possible. To increase the switching speed, the bit-cell can be designed so that rather than turning the current in each flip-flop transistor ON and OFF, a fixed current is steered from one flip-flop transistor to the other. Logic circuitry, such as a bit-cell, whose operation is based on the principle of current steering is frequently called current-mode logic.
One method of operating a bit-cell in the current-mode is to differentially connect the flip-flop transistors. For example, the emitters of the transistors may be connected together and coupled to a relatively constant current source. While this topology speeds up the bit-cell, it may increase the potential for alpha particle noise instability and saturation.
Alpha particles induce noise in semi-conductor materials by disturbing the generation and recombination of charge carriers. This noise shows up as current fluctuations in conduction currents. With the bit-cell current-mode operated, the voltage swings across the load resistors of the bit-cell transistors are reduced because of the voltage dropped by the constant-current source. Alpha particles may then generate enough current fluctuations so that the voltage across the load resistor of the conducting flip-flop transistor drops enough to cause the bit-cell to change state.
One well known method of reducing alpha particle problems is to increase the voltage swing required across the load resistors for the bit-cell to change state. A common way to accomplished this is to design the bit-cell using high ohmic value load resistors. However, this solution slows down the circuit operation because transistor interelectrode capacitances must charge through these load resistances before switching can take place.
Also, the use of large value load resistors slows down circuit operation by causing saturation of the transistors. Saturation occurs when charges are injected into the base-collector junction when the base-collector junction becomes forward biased. As explained in more detail below, to maximize bit-cell operating speed the flip-flop transistors must not saturate since the injected charges become stored and must be recombined or removed before the saturated transistor can stop conducting.
Logic designs which prevent flip-flop transistors from saturating are well known. One common method is to connect the bit-cell load resistors in parallel with devices that can dump current into the collector. This prevents the collector-base junction from becoming forward biased. A common method of doing this is to use P-N junction diodes in parallel with the load resistors of the flip-flop transistors. However, this design shows limited improvement in switching speeds because the P-N junction diodes themselves store charges in their junction, if it becomes forward biased, which must be removed before switching. Use of Schottky diodes instead of P-N junction diodes solves the saturation problem since Schottky diodes cannot accumulate charges. However, the inclusion of Schottky diodes increases the difficulty of fabricating the cell on a semiconductor wafer.
As mentioned above, cells are made by adding methods to WRITE and READ the bit-cell. When designing cells, tradeoffs involving cell READ and WRITE access times, switching speeds, dynamic range, power dissipation, cell size, cell fabrication complexity, noise margins, external circuit complexity, and many other parameters must be made to achieve the optimal design for a given application. As indicated earlier however, when high speed is required a non-saturating current-mode logic bit-cell is preferred. For optimum cell operation, the bit-cell transistors must be stable, not saturate, and have low resistances in series with interelectrode capacitances.
In conventional cells, saturation of the bit-cell tends to occur during a WRITE operations. This is because a WRITE operation requires the highest current through the load resistor of the conducting transistor and therefore may lower the collector voltage of the conducting transistor enough to forward bias the collector-base junction.
In a conventional cell, a READ or WRITE of the logic state of the bit-cell is performed using the same access path to the bit-cell. In some applications this is undesirable since overall functional operating speed may be increased and/or external circuit complexity may be reduced if independent READ and WRITE access lines to the bit-cell are available. Additionally, separate READ and WRITE access lines would be needed to enable concurrent reading and writing of memory cells.
A RAM cell design is known, shown in U.S. Pat. No. 4,701,883, that has separate READ and WRITE signal lines. However, this cell cannot be used in RAM devices where a simultaneous READ of one word and a WRITE of another is desired. This follows because a RAM device using the 4,701,883 cell would connected READ and WRITE data lines of the cell to the corresponding data lines of many similar cells. If simultaneous READ and WRITE operations were to occur, input power would have to be applied to the word lines of the words being written and read. When writing one word, the second word, attempting to be read, would be over-written.